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Draw a schematic of SSI and MSI components first, 7400 series parts before writing any code. #Mux 4x1 verilog programme by using 2x1 test bench softwareYou write Verilog like you want it to be Python, C, C++ or some other software programming language. #Mux 4x1 verilog programme by using 2x1 test bench codeDo you ever look at your code or are we supposed to be your proof readers? I noticed your add task is missing an input you have in the locations where it is used, namely cin is not on the task definition. If you are a student in school then you are definitely not being taught anything useful for real world designs. ![]() You're probably using some crappy "editor" like windows notepad (sucks) or wordpad (sucks even more).Ĭlick to expand.Only one person on edaboard would agree with the use of a task in synthesizable code (I don't agree and think it is never appropriate). You should also learn to proof read you code before posting these are ALL easy to spot mistakes.īTW, you should use an editor that has syntax highlighting, then you wouldn't have the problems with incorrect keywords like the elseif. Maybe you should learn Verilog syntax before writing code. Line 33: what is sel it's not defined in your tmux module. Also learn to indent code, haven't you ever written C and been told to indent stuff? Use whitespace in your code from now on it's free (or nearly so) and it makes code much easier to read, instead of a packed messes of characters you have to really look at to determine if something starts or ends. Lines 29-33: #10a, etc might not even compile correctly as there is no white space separating the number from the signal name. s is the bus name and using your silly names s0 and s1 in the testbench the connection should be. Line 25: s0 and s1 are NOT the way you define the ports for a bus. Line 12: sel is not declared and is probably supposed to be s Lines 10, 12: elseif is not a proper verilog keyword it is: else if Lines 1-4: sucky antiquated usage of pre-Verilog 2001 module port declaration syntax.Use Verilog 2001 syntax it's much cleaner and requires no repeating of the post names in two places. Re: Verilog Hardware description language ![]()
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